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White Electronic Designs
WV3HG2128M72AER-D6
ADVANCED*
2GB - 2x128Mx72 DDR2 SDRAM REGISTERED, w/PLL
FEATURES
240-pin, dual in-line memory module Fast data transfer rates: PC2-4200 and PC2-3200 Utilizes 533 and 400 Mb/s DDR2 SDRAM components VCC = VCCQ = 1.8V 0.1V VCCSPD = 1.7V to 3.6V JEDEC standard 1.8V I/O (SSTL_18-compatible) Differential data strobe (DQS, DQS#) option Four-bit prefetch architecture DLL to align DQ and DQS transitions with CK Multiple internal device banks for concurrent operation Supports duplicate output strobe (RDQS/RDQS#) Programmable CAS# latency (CL): 3 and 4 Adjustable data-output drive strength On-die termination (ODT) Serial Presence Detect (SPD) with EEPROM 64ms: 8,192 cycle refresh Gold edge contacts Product is lead-free RoHS compliant Dual Rank Package option * 240 Pin DIMM * PCB - 29.97mm (1.18")
* This product is under development, is not qualified or characterized and is subject to change or cancellation without notice. NOTE: Consult factory for availability of: * Vendor source control options * Industrial temperature option
DESCRIPTION
The WV3HG2128M72AER is a 128Mx72 Double Data Rate DDR2 SDRAM high density module. This memory module consists of thirty six 128Mx4 bit with 4 banks DDR2 Synchronous DRAMs in FBGA packages, mounted on a 240-pin DIMM FR4 substrate.
OPERATING FREQUENCIES
PC2-3200 Clock Speed CL-tRCD-tRP 200MHz 3-3-3 PC2-4200 266MHz 4-4-4
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PIN CONFIGURATION
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Symbol VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS RESET# NC VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DQS3# DQS3 VSS DQ26 DQ27 VSS CB0 CB1 VSS DQS8# DQS8 VSS CB2 CB3 VSS VCCQ CKE0 VCC NC NC VCCQ A11 A7 VCC A5 Pin No. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Symbol A4 VCCQ A2 VCC VSS VSS VCC NC VCC A10/AP BA0 VCCQ WE# CAS# VCCQ CS1# ODT1 VCCQ VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DQS5# DQS5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS SA2 NC VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DQS7# DQS7 VSS DQ58 DQ59 VSS SDA SCL Pin No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 Symbol VSS DQ4 DQ5 VSS DQS9 DQS9# VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DQS10 DQS10# VSS NC NC VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DQS11 DQS11# VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS12 DQS12# VSS DQ30 DQ31 VSS CB4 CB5 VSS DQS17 DQS17# VSS CB6 CB7 VSS VCCQ CKE1 VCC NC NC VCCQ A12 A9 VCC A8 A6 Pin No. 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 Symbol VCCQ A3 A1 VCC CK0 CK0# VCC A0 VCC BA1 VCCQ RAS# S0# VCCQ ODT0 A13 VCC VSS DQ36 DQ37 VSS DQS13 DQS13# VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS14 DQS14# VSS DQ46 DQ47 VSS DQ52 DQ53 VSS NC NC VSS DQS15 DQS15# VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS16 DQS16# VSS DQ62 DQ63 VSS VCCSPD SA0 SA1 2
WV3HG2128M72AER-D6
ADVANCED*
PIN NAMES
Pin Name A0-A13 BA0,BA1 DQ0-DQ63 CB0-CB7 DQS0-DQS17 DQS0#-DQS17# ODT0, ODT1 CK0,CK0# CKE0, CKE1 CS0#, CSI# RAS# CAS# WE# SA0-SA2 VCC VCCQ VSS A10/AP VREF VCCSPD NC Function Address Inputs SDRAM Bank Address Data Input/Output Check Bits Data strobes Data strobes complement On-die termination control Clock Inputs, positive line Clock Enables Chip Selects Row Address Strobe Column Address Strobe Write Enable SPD Address Core and I/O Power (1.8V) I/O Power (1.8V) Ground Address input/ autoprecharge Input/Output Reference SPD Power Spare pins, No connect
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WV3HG2128M72AER-D6
ADVANCED*
FUNCTIONAL BLOCK DIAGRAM
VSS RCS1# RCS0# DQS0 DQS0# DQD DQ1 DQ2 DQ3 DQS1 DQS1# DQ8 DQ9 DQ10 DQ11 DQS2 DQS2# DQ16 DQ17 DQ18 DQ19 DQS3 DQS3# DQ24 DQ25 DQ26 DQ27 DQS4 DQS4# DQ32 DQ33 DQ34 DQ35 DQS5 DQS5# DQ40 DQ41 DQ42 DQ43 DQS6 DQS6# DQ48 DQ49 DQ50 DQ51 DQS7 DQS7# DQ56 DQ57 DQ58 DQ59 DQS8 DQS8# CB0 CB1 CB2 CB3 DM I/O 0 I/O 1 I/O 2 I/O 3 CS# DQS DQS# DM I/O 0 I/O 1 I/O 2 I/O 3 CS# DQS DQS# CB4 CB5 CB6 CB7 DM I/O 0 I/O 1 I/O 2 I/O 3 CS# DQS DQS# DM I/O 0 I/O 1 I/O 2 I/O 3 CS# DQS DQS# DQ60 DQ61 DQ62 DQ63 DQS17 DQ17# DM I/O 0 I/O 1 I/O 2 I/O 3 CS# DQS DQS# DM I/O 0 I/O 1 I/O 2 I/O 3 CS# DQS DQS# DM I/O 0 I/O 1 I/O 2 I/O 3 CS# DQS DQS# DM I/O 0 I/O 1 I/O 2 I/O 3 CS# DQS DQS# DQ52 DQ53 DQ54 DQ55 DQS16 DQ16# DM I/O 0 I/O 1 I/O 2 I/O 3 CS# DQS DQS# DM I/O 0 I/O 1 I/O 2 I/O 3 CS# DQS DQS# DM I/O 0 I/O 1 I/O 2 I/O 3 CS# DQS DQS# DM I/O 0 I/O 1 I/O 2 I/O 3 CS# DQS DQS# DQ44 DQ45 DQ46 DQ47 DQS15 DQ15# DM I/O 0 I/O 1 I/O 2 I/O 3 CS# DQS DQS# DM I/O 0 I/O 1 I/O 2 I/O 3 CS# DQS DQS# DM I/O 0 I/O 1 I/O 2 I/O 3 CS# DQS DQS# DM I/O 0 I/O 1 I/O 2 I/O 3 CS# DQS DQS# DQ36 DQ37 DQ38 DQ39 DQS14 DQS14# DM I/O 0 I/O 1 I/O 2 I/O 3 CS# DQS DQS# DM I/O 0 I/O 1 I/O 2 I/O 3 CS# DQS DQS# DM I/O 0 I/O 1 I/O 2 I/O 3 CS# DQS DQS# DM I/O 0 I/O 1 I/O 2 I/O 3 CS# DQS DQS# DQ28 DQ29 DQ30 DQ31 DQS13 DQS13# DM I/O 0 I/O 1 I/O 2 I/O 3 CS# DQS DQS# DM I/O 0 I/O 1 I/O 2 I/O 3 CS# DQS DQS# DM I/O 0 I/O 1 I/O 2 I/O 3 CS# DQS DQS# DM I/O 0 I/O 1 I/O 2 I/O 3 CS# DQS DQS# DQ20 DQ21 DQ22 DQ23 DQS12 DQS12# DM I/O 0 I/O 1 I/O 2 I/O 3 CS# DQS DQS# DM I/O 0 I/O 1 I/O 2 I/O 3 CS# DQS DQS# DM I/O 0 I/O 1 I/O 2 I/O 3 CS# DQS DQS# DM I/O 0 I/O 1 I/O 2 I/O 3 CS# DQS DQS# DQ12 DQ13 DQ14 DQ15 DQS11 DQS11# DM I/O 0 I/O 1 I/O 2 I/O 3 CS# DQS DQS# DM I/O 0 I/O 1 I/O 2 I/O 3 CS# DQS DQS# DM I/O 0 I/O 1 I/O 2 I/O 3 CS# DQS DQS# DM I/O 0 I/O 1 I/O 2 I/O 3 CS# DQS DQS# DQ4 DQ5 DQ6 DQ7 DQS10 DQS10# DM I/O 0 I/O 1 I/O 2 I/O 3 CS# DQS DQS# DM I/O 0 I/O 1 I/O 2 I/O 3 CS# DQS DQS# DQS9 DQS9# DM I/O 0 I/O 1 I/O 2 I/O 3 CS# DQS DQS# DM I/O 0 I/O 1 I/O 2 I/O 3 CS# DQS DQS#
CS0# CS1# BA0 - BA1 A0 - A13 RAS# CAS# WE# CKE0 CKE1 ODT0 ODT1 RESET# PCK7 PCK7#
1:4 R E G I S T E R
RST#
RCS0# RCS1#
CS#: DDR2 SDRAMs CS#: DDR2 SDRAMs BA0-BA1 : DDR2 SDRAMs A0-A13 : DDR2 SDRAMs
SCL
Serial PD SDA WP A0 A1 A2
VCCSPD VCC/VCCQ VREF
Serial PD DDR2 SDRAMs DDR2 SDRAMs DDR2 SDRAMs
RBA0-RBA1# RA0-RA13 RRAS# RCAS# RWE# RCKE0 RCKE1 RODT0 RODT1
RAS# : DDR2 SDRAMs CAS#: DDR2 SDRAMs WE#: DDR2 SDRAMs CKE : DDR2 SDRAMs CKE : DDR2 SDRAMs DDR2 SDRAMs DDR2 SDRAMs
CK0# RESET# CK0
SA0 SA1 SA2
VSS
P L L
OE
PCK0-PCK6, PCK8, PCK9
CK : DDR2 SDRAMs CK# : DDR2 SDRAMs
PCK0#-PCK6#, PCK8#, PCK9# PCK7 CK : Register PCK7# CK# : Register
NOTE: All resistor values are 22 ohms unless otherwise specified.
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All voltages referenced to VSS Parameter Supply voltage I/O Supply voltage VCCL Supply voltage I/O Reference voltage I/O Termination voltage Symbol VCC VCCQ VCCL VREF VTT Min 1 .7 1 .7 1 .7 0.49 x VCCQ VREF-0.04 Typical 1 .8 1 .8 1 .8 0.50 x VCCQ VREF
WV3HG2128M72AER-D6
ADVANCED*
DC OPERATING CONDITIONS
Max 1 .9 1 .9 1 .9 0.51 x VCCQ VREF + 0.04 Unit V V V V V Notes 1 4 4 2 3
Notes: 1. VCC VCCQ must track each other. VCCQ must be less than or equal to VCC. 2. VREF is expected to equal VCCQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed 1 percent of the DC value. Peak-to-peak AC noise on VREF may not exceed 2 percent of VREF. This measurement is to be taken at the nearest VREF bypass capacitor. 3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. 4. VCCQ tracks with VCC; VCCL track with VCC.
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VCCQ VCCL VIN, VOUT TSTG Parameter Voltage on VCC pin relative to VSS Voltage on VCCQ pin relative to VSS Voltage on VCCL pin relative to VSS Voltage on any pin relative to VSS Storage temperature Input leakage current; Any input 0VIL
-5
5
uA
IOZ IVREF
-10 -72
-10 72
uA uA
CAPACITANCE
TA=25C, f=1MHz, VCC =VCCQ = 1.8V Parameter Input capacitance (A0 ~ A1 3, BA0 ~ BA1 ,RAS#,CAS#,WE#) Input capacitance ( CKE0, CKE1), (ODT0, ODT1) Input capacitance (CS0#, CS1#) Input capacitance (CK0, CK0#) Input capacitance (DQS0 ~ DQS8) Input capacitance (DQ0 ~ DQ63), (CB0 ~ CB7) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 COUT1 Min 9 9 14 6 9 9 Max 11 11 18 7 12 12 Unit pF pF pF pF pF pF
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WV3HG2128M72AER-D6
ADVANCED*
OPERATING TEMPERATURE CONDITION
Parameter Operating temperature Symbol TOPER Rating 0 to 85 Units C Notes 1, 2
Notes: 1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JEDEC JESD51 .2 2. At 0 - 85C, operation temperature range, all DRAM specification will be supported.
INPUT DC LOGIC LEVEL
All voltages referenced to VSS Parameter Input High (Logic 1 ) Voltage Input Low (Logic 0) Voltage Symbol VIH(DC) VIL(DC) Min VREF + 0.1 25 -0.300 Max VREF + 0.300 VREF - 0.125 Unit V V
INPUT AC LOGIC LEVEL
All voltages referenced to VSS Parameter AC Input High (Logic 1 ) Voltage AC Input Low (Logic 0) Voltage DDR2-400 & DDR2-533 Symbol VIH(AC) VIL(AC) Min VREF + 0.250 -- Max -- VREF - 0.250 Unit V V
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Includes DDR2 SDRAM components only Symbol IDD0* Proposed Conditions
WV3HG2128M72AER-D6
ADVANCED*
DDR2 IDD SPECIFICATIONS AND CONDITIONS
534 2284 403 2284 Units mA
Operating one bank active-precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating one bank active-read-precharge current; IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus input are switching; Data pattern is same as IDD6W Precharge power-down current; All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge quiet standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Active power-down current; All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Fast PDN Exit MRS(12) = 0mA Slow PDN Exit MRS(12) = 1mA
IDD1*
2554
2554
mA
IDD2P**
988
988
mA
IDD2Q**
1780
1780
mA
IDD2N**
1960 1780 1132 2500
1960 1780 1132 2500
mA mA mA mA
IDD3P**
IDD3N**
Active standby current; All banks open; tCK = tCK(IDD), tRC = tRC(IDD); tRAS = tRASmax(IDD); CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W Burst auto refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Self refresh current; CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING Normal
IDD4W*
2824
2644
mA
IDD4R*
2914
2734
mA
IDD5**
5740
5740
mA
IDD6**
288
288
mA
IDD7*
Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data bus imputs are switching.
4804
4804
mA
Notes: IDD specification is based on SAMSUNG components. Other DRAM manufacturers specification may be different. * Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P ( CKE LOW) mode. ** Value calculated reflects all module ranks in this operating condition.
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WV3HG2128M72AER-D6
ADVANCED*
AC TIMING PARAMETERS & SPECIFICATIONS
0C TA +70C; VCCQ = + 1.8V 0.1V, VCC = +1.8V 0.1V AC CHARACTERISTICS PARAMETER CL = 4 Clock cycle time CL = 3 Clock CK high-level width CK low-level width Half clock period Clock jitter DQ output access time from CK/CK# Data-out high-impedance window from CK/CK# Data-out low-impedance window from CK/CK# DQ and DM input setup time relative to DQS Data DQ and DM input hold time relative to DQS A DQ and DM input pulse width (for each input) Data hold skew factor DQ...DQS hold, DQS to first DQ to go nonvalid, per access Data valid output window (DVW) DQS input high pulse width DQS input low pulse width DQS output access time from CK/CK# DQS falling edge to CK rising ... setup time DQS falling edge from CK rising ... hold time Data Strobe DQS...DQ skew, DQS to last DQ valid, per group, per access DQS read preamble DQS read postamble DQS write preamble setup time DQS write preamble DQS write postamble Write command to first DQS latching transition Notes:
AC specification is based on SAMSUNG components. Other DRAM manufacturers specification may be different. Continued on next page
534 SYMBOL tCK (4) tCK (3) tCH tCL tHP tJIT tAC tHZ tLZ tDS tDH tDIPW tQHS tQH tDVW tDQSH tDQSL tDQSCK tDSS tDSH tDQSQ tRPRE tRPST tWPRES tWPRE tWPST tDQSS 0.9 0.4 0 0.35 0.4 WL - 0.25 0.6 WL + 0.25 tHP - tQHS tQH - tDQSQ 0.35 0.35 -450 0.2 0.2 300 1.1 0.6 0.9 0.4 0 0.35 0.4 WL - 0.25 +450 tAC MIN 100 225 0.35 400 tHP - tQHS tQH - tDQSQ 0.35 0.35 -500 0.2 0.2 MIN 3,750 5,000 0.45 0.45 MIN (tCH, tCL) TBD -500 +500 tAC MAX tAC MAX tAC MIN 150 275 0.35 MAX 8,000 8,000 0.55 0.55 MIN 5,000 5,000 0.45 0.45
403 MAX 8,000 8,000 0.55 0.55 UNIT ps ps tCK tCK ps ps +600 tAC MAX tAC MAX ps ps ps
MIN (tCH, tCL) TBD -600
tCK 450 ps ps ns tCK tCK +500 ps tCK tCK 350 1.1 0.6 ps tCK tCK ps tCK 0.6 WL + 0.25 tCK tCK
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WV3HG2128M72AER-D6
ADVANCED*
AC TIMING PARAMETERS (cont'd)
0C TA +70C; VCCQ = + 1.8V 0.1V, VCC = +1.8V 0.1V AC CHARACTERISTICS PARAMETER Address and control input pulse width for each input Address and control input setup time Address and control input hold time CAS# to CAS# command delay ACTIVE to ACTIVE (same bank) command ACTIVE bank a to ACTIVE bank b command ACTIVE to READ or WRITE delay Four Bank Activate period ACTIVE to PRECHARGE command Internal READ to precharge command delay Write recovery time Auto precharge write recovery + precharge time Internal WRITE to READ command delay PRECHARGE command period PRECHARGE all command period LOAD MODE command cycle time CKE low to CK,CK# uncertainty REFRESH to REFRESH command interval Self Refresh Average periodic refresh interval Exit self refresh to non-READ command Exit self refresh to READ command Exit self refresh timing reference ODT turn-on delay ODT turn-on ODT turn-off delay ODT turn-off ODT ODT turn-on (power-down mode) SYMBOL tIPW tIS tIH tCCD tRC tRRD tRCD tFAW tRAS tRTP tWR tDAL tWTR tRP tRPA tMRD tDELAY tRFC tREFI tXSNR tXSRD tISXR tAOND tAON tAOFD tAOF tAONPD MIN 0.6 250 375 2 60 7.5 15 37.5 45 7.5 15 tWR + tRP 7.5 15 tRP + tCK 2 4.375 127.5 tRFC (MIN) + 10 200 tIS 2 tAC (MIN) 2.5 tAC (MIN) tAC (MIN) + 2000 tAC (MIN) + 2000 3 8 2 6 - AL 2 3 534 MAX MIN 0.6 250 475 2 65 7.5 15 37.5 45 7.5 15 tWR + tRP 10 15 tRP + tCK 2 4.375 127.5 tRFC (MIN) + 10 200 tIS 2 tAC (MIN) 2.5 tAC (MIN) tAC (MIN) + 2000 tAC (MIN) + 2000 3 8 2 6 - AL 2 3 403 MAX UNIT tCK ps ps tCK ns ns ns ns ns ns ns ns ns ns ns tCK ns ns s ns tCK ps tCK ps tCK ps ps
Command and Address
37.5 70,000
37.5 70,000
70,000 7.8
70,000 7.8
ODT turn-off (power-down mode) ODT to power-down entry latency ODT power-down exit latency Exit active power-down to READ command, MR[bit12=0] Exit active power-down to READ command, MR[bit12=1] A Exit precharge power-down to any non-READ command. CKE minimum high/low time
tAOFPD tANPD tAXPD tXARD tXARDS tXP tCKE
2 tAC (MAX) + 1000 2.5 tAC (MAX) + 600 2 x tCK + tAC (MAX) + 1000 2.5 x tCK + tAC (MAX) + 1000
2 tAC (MAX) + 1000 2.5 tAC (MAX) + 600 2 x tCK + tAC (MAX) + 1000 2.5 x tCK + tAC (MAX) + 1000
ps tCK tCK tCK tCK tCK tCK
Notes: AC specification is based on SAMSUNG components. Other DRAM manufacturers specification may be different.
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Power-Down
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WV3HG2128M72AER-D6
ADVANCED*
ORDERING INFORMATION FOR D6
Part Number WV3HG2128M72AER534D6xG WV3HG2128M72AER403D6xG Speed 266MHz/533Mb/s 200MHz/400Mb/s CAS Latency 4 3 tRCD 4 3 tRP 4 3 Height* 29.97mm (1.18") 29.97mm (1.18")
NOTES: * RoHS products. ("G" = RoHS Compliant) * Vendor specific part numbers are used to provide memory component source control. The place holder for this is shown as a lower case "x" in the part numbers above and is to be replaced with respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others) * Consult factory for availability of industrial temperature (-40C to 85C) option
PACKAGE DIMENSIONS FOR D6
Front View
3.00 (0.118) (4x)
133.35 (5.25) 133.20 (5.244)
30.50 (1.201) 29.85 (1.175)
Detail C
17.80 (0.700) TYP.
5.175 (0.204) (2x)
PIN 1
4.843 (123.0) TYP.
10.00 (0.394) TYP.
4.00 (0.157) MAX
Back View
PIN 120
PIN 240
3.80 (0.150)
PIN 121
63.00 (2.48) TYP
5.0 (0.197) TYP.
55.00 (2.165) TYP
Detail B
3.00 (0.118) (4X)
Detail A
1.37 (0.054) 1.17 (0.046)
5.00 (0.197) TYP.
2.70 (0.106 2.30 (0.091)
0.85 (0.034) 0.75 (0.030)
0.20 (0.008) 2.50 (0.098) 1.69 0 (0.063) 1.40 (0.055) 4.00 (0.157) (4X)
1.00 (0.039)
Detail A
Detail B
Detail C
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
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WV3HG2128M72AER-D6
ADVANCED*
PART NUMBERING GUIDE
WV 3 H G 2 128M 72 A E R xxx D6 x G
WEDC MEMORY (SDRAM) DDR 2 GOLD RANK DEPTH BUS WIDTH COMPONENT WIDTH (x4) 1.8V REGISTERED SPEED (MHz) PACKAGE 240 PIN COMPONENT VENDOR NAME (M = Micron) (S = Samsung) G = ROHS COMPLIANT
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Document Title
2GB - 2x128Mx72 DDR2 SDRAM REGISTERED, w/PLL
WV3HG2128M72AER-D6
ADVANCED*
Revision History Rev #
Rev 0
History
Created
Release Date
September 2005
Status
Advanced
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